NERSC Signs Contract with SDSC to Help Evaluate Tera Machine

Published 08/05/1998

For more information, contact:
Jon Bashor, NERSC, bashor@lbl.gov
Ann Redelfs, NPACI/SDSC, redelfs@sdsc.edu

BERKELEY, CA -- After several months of negotiation, the National Energy Research Scientific Computing Center (NERSC) has signed an agreement with the SDSC to evaluate potential applications of the Tera MTA (Multi-Threaded Architecture) supercomputer recently installed at SDSC. The agreement, which went into effect last month, gives NERSC researchers 20 percent of computer time available to users of the two-processor system, which was accepted in April, as well as 20 percent of the time available when the system is upgraded to four processors.

SDSC's Tera is the first machine delivered by Seattle-based Tera Computer Company. The computer uses a unique multi-threaded architecture which combines the large shared memory of a vector computer with the potential scalability distributed-memory parallel machines. The Tera design seeks to overcome the "latency" problem, which is wasted time when moving information between processors and memory. This latency can prevent a parallel machine from achieving high performance.

The MTA compiler divides the program being run into threads, then assigns the threads to the processors, which can each execute up to 128 threads concurrently. The processors can keep a large number of memory references in progress at once, so that while one thread is waiting for memory, another thread can be run. The MTA system is scalable, which means that it provides increases in application performance proportional to the number of processors with no change in the programming model or source code.

"If the Tera MTA works as designed, it could deliver higher system utilization and higher execution speeds than other parallel machines," said Sid Karin, Director of SDSC and the National Partnership for Advanced Computational Infrastructure (NPACI).

The Tera machine is also different in that it was developed from the software up, rather than in the "hardware first" method typically used in building new computers.

"Parallel programming, or writing programs intended for parallel execution, may be one of the most complex endeavors ever attempted by humans," said NERSC's Tom DeBoni, who did most of the legwork in setting up the contract. "Any tool, be it hardware, software, or mathematics, that eases the burden this complexity places on the programmers of parallel applications will be a boon to all forms of computation, especially scientific computation."

Because of the unique design and its potential, SDSC's deployment of the Tera is being supported and evaluated by the National Science Foundation and the Defense Advanced Research Projects Agency. DOE is also interested in the architecture and is funding NERSC's contract with SDSC. The contract, valued at $1,000,000, covers the period through May 31,1999, and consists of several phases.

"The DOE Mathematical, Information and Computational Sciences Office is proud to have the new research group at NERSC participate in this interagency research project," said Tom Kitchens, the NERSC program manager in the MICS Office. "The project will develop a better and detailed assessment of the ramifications to scientific applications of the MTA concept and its first substantial embodiment -- the Tera. I believe the ease of use and scalability -- and ultimately performance -- could make MTA very popular with engineers and scientists. For that reason, we are very interested in assessing this technology."

"We are delighted that NERSC is joining us in this project, "said Karin, "as they will bring a new set of applications to the endeavor, as well as a different perspective."

According to the contract, "It is expected that under this Phase I Participation Level, NERSC researchers will be able to use the MTA system hardware and software as it becomes available, and will assist in testing and acceptance work conducted by SDSC researchers on the MTA system. It is further expected that as NERSC researchers gain experience with the system, they will be able to perform runs independently, subject to any software license restrictions imposed on specific applications. Ultimately, NERSC researchers will be able to edit, instrument, compile, debug and run codes on the MTA system and hence conduct a thorough study of applications including the quantification of performance on the MTA and quantification of the programming efforts necessary to achieve superior run performance."

The Tera project is one of several collaborations NERSC is undertaking as a partner in NPACI, which is led by SDSC.

For information on initial tests of the Tera by SDSC researchers, visit http://www.cs.ucsd.edu/users/carter/Tera/tera.html.